Specifies the use of instruction scheduling optimization.

This pragma is compatible with the following platform targets:

68K

PowerPC

NEC V800

Intel x86

MIPS

Embedded 68K

This pragma lets you choose how the compiler rearranges instructions to increase speed. Some instructions, such as a memory load, take more than one processor cycle. By moving an unrelated instruction between the load and the instruction that uses the loaded item, the compiler saves a cycle when executing the program.

For PowerPC, you can use the 401, 403, 505, 555, 601, 602, 603, 604, 740, 750, 801, 821, 823, 850, 860, 8240, 8260, altivec, PPC603e, PPC604e, PPC403GA, PPC403GB, PPC403GC, PPC403GCX.

However, if you're debugging your code, turn this pragma off. Since it rearranges the instructions produced from your code, the debugger will not be able to match the statements in your source code to the produced instructions.